In recent years, a shortening of the gate length of a memory cell transistor is necessary because a reduction of a cell size is required in a DRAM (Dynamic Random Access Memory). However, if the gate length is smaller, then the short channel effect of the transistor becomes greater, and sub-threshold current disadvantageously increases. Furthermore, if substrate concentration is increased in order to suppress an increase in the sub-threshold current, junction leakage increases. As a result, the DRAM is confronted with a serious problem of deteriorated refresh characteristics.
To avoid the problem, attention has been paid to a so-called trench-gate transistor (also “recess-channel transistor”) configured so that a gate electrode is buried in a groove formed in a semiconductor substrate (see Japanese Patent Application Laid-open Nos. H9-232535, 2001-210801, 2005-142203, H7-66297, and 2004-14696). The trench-gate transistor can sufficiently secure an effective channel length (a gate length) and enables achieving a fine DRAM having a minimum machining dimension of 90 nm or less.
However, the conventional trench-gate transistor has the following problem. Although the short channel effect can be suppressed, further improvement is necessary for increasing drive current, reducing parasitic capacitance and the like to improve circuit delay.